Design of Ultra-low Leakage Power Sequential Circuits

Reduction in leakage power has become an important concern in low-voltage, low-power, and highperformance applications. International Technology Roadmap for Semiconductors projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. A novel approach for ultra-low leakage CMOS circuit structure is “Sleepy keeper.” Sleepy keeper uses traditional sleep transistors plus two additional transistors – driven by a gate’s already calculated output – to save state during sleep mode. Dual Vth values can be applied to sleepy keeper in order to dramatically reduce sub-threshold leakage current. Unlike many other previous approaches, sleepy keeper can retain logic state during sleep mode while achieving ultra-low leakage power consumption. For applications spending the vast majority of time in sleep or standby mode, requires low area, high performance and maintenance of exact logic state, the sleepy keeper approach provides a new weapon.